Cortex_hercules: Introduce preliminary cpu support

Change-Id: Iab767e9937f5c6c8150953fcdc3b37e8ee83fa63
Signed-off-by: Louis Mayencourt <[email protected]>

diff --git a/include/lib/cpus/aarch64/cortex_hercules.h b/include/lib/cpus/aarch64/cortex_hercules.h
new file mode 100644 (file)
index 0000000..86e8af0
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_hercules.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_HERCULES_H
+#define CORTEX_HERCULES_H
+
+#include <lib/utils_def.h>
+
+#define CORTEX_HERCULES_MIDR                                   U(0x410FD410)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_HERCULES_CPUECTLR_EL1                           S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_HERCULES_CPUPWRCTLR_EL1                         S3_0_C15_C2_7
+#define CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT       U(1)
+
+#endif /* CORTEX_HERCULES_H */

diff --git a/lib/cpus/aarch64/cortex_hercules.S b/lib/cpus/aarch64/cortex_hercules.S
new file mode 100644 (file)
index 0000000..25287de
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_hercules.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_hercules.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+       /* ---------------------------------------------
+        * HW will do the cache maintenance while powering down
+        * ---------------------------------------------
+        */
+func cortex_hercules_core_pwr_dwn
+       /* ---------------------------------------------
+        * Enable CPU power down bit in power control register
+        * ---------------------------------------------
+        */
+       mrs     x0, CORTEX_HERCULES_CPUPWRCTLR_EL1
+       orr     x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+       msr     CORTEX_HERCULES_CPUPWRCTLR_EL1, x0
+       isb
+       ret
+endfunc cortex_hercules_core_pwr_dwn
+
+       /*
+        * Errata printing function for cortex_hercules. Must follow AAPCS.
+        */
+#if REPORT_ERRATA
+func cortex_hercules_errata_report
+       ret
+endfunc cortex_hercules_errata_report
+#endif
+
+       /* ---------------------------------------------
+        * This function provides cortex_hercules specific
+        * register information for crash reporting.
+        * It needs to return with x6 pointing to
+        * a list of register names in ascii and
+        * x8 - x15 having values of registers to be
+        * reported.
+        * ---------------------------------------------
+        */
+.section .rodata.cortex_hercules_regs, "aS"
+cortex_hercules_regs:  /* The ascii list of register names to be reported */
+       .asciz  "cpuectlr_el1", ""
+
+func cortex_hercules_cpu_reg_dump
+       adr     x6, cortex_hercules_regs
+       mrs     x8, CORTEX_HERCULES_CPUECTLR_EL1
+       ret
+endfunc cortex_hercules_cpu_reg_dump
+
+declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
+       CPU_NO_RESET_FUNC, \
+       cortex_hercules_core_pwr_dwn

diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index bd6812b797699d1c74d6597ccd9970a2e012ff11..5fc9983b01b3b5ef8788f4d0015bd246a998c91d 100644 (file)
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -112,7 +112,8 @@ else
                                        lib/cpus/aarch64/cortex_a77.S           \
                                        lib/cpus/aarch64/neoverse_n1.S          \
                                        lib/cpus/aarch64/neoverse_e1.S          \
-                                       lib/cpus/aarch64/neoverse_zeus.S
+                                       lib/cpus/aarch64/neoverse_zeus.S        \
+                                       lib/cpus/aarch64/cortex_hercules.S
        # AArch64/AArch32
        else
                FVP_CPU_LIBS    +=      lib/cpus/aarch64/cortex_a55.S           \